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ICT COST Action IC1202
Timing Analysis on Code-Level (TACLe)

Embedded systems increasingly permeate our daily lives. Many of those systems are business- or safety-critical, with strict timing requirements. Code-level timing analysis (used to analyse software running on some given hardware w.r.t. its timing properties) is an indispensable technique for ascertaining whether or not these requirements are met. However, recent developments in hardware, especially multi-core processors, and in software organisation render analysis increasingly more difficult, thus challenging the evolution of timing analysis techniques. New principles for building "timing-composable" embedded systems are needed in order to make timing analysis tractable in the future. This requires improved contacts within the timing analysis community, as well as with related communities dealing with other forms of analysis such as model-checking and type-inference, and with computer architectures and compilers. The goal of this Action is to gather these forces in order to develop industrial-strength code-level timing analysis techniques for future-generation embedded systems.

(Descriptions are provided by the Actions directly via e-COST.)

General Information*

Chair of the Action:

Prof Björn LISPER (SE)

Vice Chair of the Action:

Prof Heiko FALK (DE)

Science officer of the Action:


Administrative officer of the Action:



Action Fact Sheet

Download AFS as .RTF

Memorandum of Understanding

Download MoU as PDF

Progress Report

Download Progress Report as PDF


Download Poster as PDF

Final Achievement Report

Download Final Achievement Report as PDF


Action website:

* content provided by e-COST.
Data is synchronised once per night.


Last updated: 09 June 2012 top of page